1. Field
The present disclosure relates to a semiconductor device, and in particular to a technology effective in application to a semiconductor device integrated with field effect transistors having an offset gate structure.
2. Description of Related Art
A lateral power MOSFET, for example, is known as a power transistor used in a power amplifier circuit, a power supply circuit, a converter, or a power supply protection circuit. Japanese Unexamined Patent Application Publication No. 2003-324159 discloses a lateral power MOSFET in which high electric field relaxation for achieving a high withstand voltage is performed by forming a field insulation film in the drain region side of a gate electrode and forming an offset region, or a drift region, with a lower impurity concentration than the drain region around the drain region.
Japanese Unexamined Patent Application Publication No. H07-288328 discloses relaxation of electric field concentration arising at a boundary between an offset region and a drain region when a depletion layer generated at the boundary of the pn junction between a channel forming region and the offset region extends, by an enhanced impurity concentration at the boundary between the offset region and the drain region.
A lateral power MOSFET has a layout in which a plurality of source regions and drain regions alternately arranged along the gate length direction, which is the direction transverse to the longitudinal direction, of a gate electrode. This arrangement is aimed at reducing an area of the device by sharing the drain region in a construction with a large channel width in order to decrease ON resistance. A gate electrode is disposed between the source region and the drain region. Each of the plurality of gate electrodes is connected together with a gate interconnection extending on a field insulation film along the transverse direction of the gate electrode at a place outside the source region and the drain region.
As to the electric field concentration arising at the offset region and at the drain region, JP H07-288328 fails to mention about the case arising only at a part of a semiconductor device due to a field plate effect of the gate inter-connection.